One type of prior NAND gate and NOR gate logic circuits typically employ complementary metal-oxide semiconductor ("CMOS") transistors. The prior NAND gate and NOR gate logic circuits are typically employed for most digital logic designs. One application for one type of prior NAND gate and NOR gate logic circuits is to form decoders or pre-decoders. Typically, NAND gate logic circuits are used to form a decoder circuit when the input signals of the decoder are active high signals. NOR gate logic circuits are used to form a decoder circuit when the input signals of the decoder are active low signals. FIG. 1 schematically illustrates the logic configuration of a prior decoder 10 that is implemented with four NAND gate logic circuits. FIG. 2 schematically illustrates the logic configuration of a prior decoder 20 that includes four NOR gate logic circuits. Each of decoders 10 and 20 of FIGS. 1 and 2, respectively, receives a binary sequence of input signals. FIGS. 1-2 each illustrates one typical implementation of a decoder using CMOS transistors. The circuit of decoder 10 of FIG. 1 is shown in FIG. 3 and the circuit of decoder 20 of FIG. 2 is shown in FIG. 4.
Referring to FIG. 3, transistors 31 through 34 form NAND gate 14 of FIG. 1. Transistors 35 through 38 form NAND gate 13 of FIG. 1. Transistors 39 through 42 form NAND gate 12 of FIG. 1 and transistors 43 through 46 form NAND gate 11 of FIG. 1. Transistors 31-32, 35-36, 39-40, and 43-44 are P-channel transistors and are connected in parallel, respectively. Transistors 33-34, 37-38, 41-42, and 45-46 are N-channel transistors and are connected in series, respectively.
Referring to FIG. 4, transistors 51 through 54 form NOR gate 21 of FIG. 2. Transistors 55 through 58 form NOR gate 22 of FIG. 2. Transistors 59 through 62 form NOR gate 23 of FIG. 2 and transistors 63-66 form NOR gate 24 of FIG. 2. Transistors 53-54, 57-58, 61-62, and 65-66 are-N-channel transistors and are connected in parallel, respectively. Transistors 51-52, 55-56, 59-60, and 63-64 are P-channel transistors and are connected in series, respectively.
One disadvantage associated with the above-mentioned prior art circuits of FIGS. 3 and 4 is that the input capacitance in each of the circuits 30 and 50 is relatively high. This is due to the fact that each of the NAND gate or NOR gate circuit is independently configured with transistors in the respective one of decoder circuits 30 and 50, This typically causes some level of redundancy in the decoder circuit because the same input signal is typically applied to different NAND or NOR gate circuits. For example, as shown in FIG. 3, transistors 34 and 38 both receive the same B input signal and transistors 42 and 46 both receive the same B input signal. Similarly in FIG. 4, transistors 51 and 55 both receive the same D input signal and transistors 59 and 63 both receive the same D input signal.
Another disadvantage associated with the above-mentioned prior art decoder circuits of FIGS. 3 and 4 is that the propagation delay for an input signal through its respective circuit is typically different than that for another input signal through the same circuit. This is typically due to the fact that some of the transistors are serially connected to receive the input signals in both the NAND gate circuit and NOR gate circuit. As can be seen in FIG. 3, transistor 45, for example, is connected between an output node 37a and ground via transistor 46. The gate of transistor 45 receives the A input signal while the gate of transistor 46 receives the B input signal. If output 37a of the NAND gate formed by transistors 43-46 is in transition from logical high to logical low due to the signal change of the B input signal (where the A input signal is already logically high), both output node 37a and the node between transistors 45 and 46 must be discharged through transistors 45 and 46. If, on the other hand, output node 37a is in transition from logical high to logical low due to the signal change of the A input signal (where the B input signal is already logically high), then only output node 37a needs to be discharged. Therefore, the propagation delay for the A input signal is less than that of the B input signal for the NAND gate formed by transistors 43-46.
Similarly, as can be seen from FIG. 4, transistor 51 is connected between the power supply and an output node 55a via transistor 52. The gate of transistor 51 receives the D input signal while the gate of transistor 52 receives the C input signal. If output node 55a of NOR gate formed by transistors 51 through 54 is in transition from logical low to logical high due to the signal change of the D input signal (where the C input signal is already logically low), both output node 55a and the node between transistors 51 and 52 must be charged through transistors 51 and 52. If, on the other hand, output node 55a is in transition from logical low to logical high due to the signal change of the C input signal (where the D input signal is already logically low), only output node 55a needs to be charged through transistors 51-52. Therefore, the circuits in FIGS. 3-4 both suffered from the unbalanced propagation delay between the input signals.